CV
Yuseon Choi
Summary
M.S. student at KAIST (Graduate School of AI Semiconductor) researching AI accelerators and hardware–algorithm co-design for generative AI.
Education
- M.S. in Graduate School of AI Semiconductor2026-08-01Korea Advanced Institute of Science and Technology (KAIST)GPA: 4.15 / 4.3
- B.S. in School of Electrical Engineering2024-08-01Korea Advanced Institute of Science and Technology (KAIST)GPA: 3.78 / 4.3 (Major GPA: 3.9 / 4.3)
PROFESSIONAL EXPERIENCE
- Semiconductor System LabMaster’s Researcher (Advisor: Hoi-Jun Yoo)
- Conducted research on digital accelerators with a focus on hardware–algorithm co-design for generative AI
- Proposed heuristic-based quantization algorithm for LLM, improving low-bit inference accuracy and hardware efficiency
- Designed an integer-based microarchitecture optimized for low-rank, rotation-based, and group-quantized workloads
- Architected a mixed-precision caching strategy for energy-efficient on-premise deployment of Mixture-of-Experts models
- Samsung ResearchIntern (Advisor: Guyeon Wei, Fellow, Professor at Harvard SEAS)
- Completed an internship at the SoC Architecture Team, Samsung Electronics DX Division R&D center
- Surveyed Processing-in-Memory (PIM) and Compute-in-Memory (CIM) paradigms for energy-efficient AI workloads
- Republic of Korea Marine CorpsCommunication & Intelligence Sergeant
- Served as a Signal Platoon Section (15 members) leader for 6 months, selected as “Distinguished Marine”
- Managed overall maintenance, repair and operation of Tactical Network and Mobile Subscriber Access Point (MSAP)
- Completed top honors in ICT education (F/AM, Satellite comm., Network) at Military Education & Training group
Skills
Programming
- Python
- Verilog
- C
- Java/Kotlin
EDA & Simulation Tools
- Synopsys Design Compiler
- Cadence Virtuoso
Publications
- EdgeDiff: 418.4mJ/inference Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization2025IEEE International Solid-State Circuits Conference (ISSCC)Conference paper presented at ISSCC 2025 (San Francisco, CA, USA; Feb. 2025).
- LightRot: A Light-weighted Rotation Scheme and Architecture for Accurate Low-bit Large Language Model Inference2025IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)Journal article in IEEE JETCAS (2025).
- GyRot: Leveraging Hidden Synergy between Rotation and Fine-grained Group Quantization for Low-bit LLM Inference2026IEEE International Symposium on High Performance Computer Architecture (HPCA)Conference paper at HPCA 2026.
- SeVeDo: A Heterogeneous Transformer Accelerator for Low-Bit Inference via Hierarchical Group Quantization and SVD-Guided Mixed Precision2026IEEE International Symposium on Circuits and Systems (ISCAS)Under review for ISCAS 2026.
- SliceMoE: Bit-Sliced Expert Caching under Miss-Rate Constraints for Efficient MoE Inference2026
Portfolio
- ISSCC 2025 Demonstration Session2025ProjectDeveloped an application integrating a Diffusion Model with hardware acceleration to support multi-modality.
- EE571 Advanced Electronic Circuits — SLAM-based Mine-clearing Robot2024ProjectBuilt a SLAM-based mine-clearing robot and implemented YOLOv5 for object detection; ranked 1st among 8 teams.
- EE405 Electronics Design Lab — AI-based Autonomous Rover / Bandgap-Reference Circuit2023ProjectDesigned a Bandgap-Reference Circuit (BGR) operating at 1.25/1.8V over -40~125°C.
Languages
- KoreanNative
- EnglishTOEFL 98
Interests
- Snowboarding
- Surfing
- Basketball
- Music